1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device for preventing plasma induced damage (PID), and a layout thereof.
2. Description of the Related Art
As the integration density of semiconductor devices increases, a pitch between patterns formed on a wafer surface is continuously reduced and an aspect ratio is gradually increased. Thus, concerns that have not previously arisen during the fabrication of semiconductor devices or have been previously unimportant are surfacing.
Among them, PID occurring during a process using plasma, for example, a deposition or etch process using plasma, degrades characteristics of a device.
PID refers to damage that is generated in a process using plasma, while electric charges trapped into a wafer are being discharged by plasma ions.
Such PID is influenced by many causes, such as ions formed by plasma and extreme ultraviolet radiation. In particular, it has been known that the charging of a wafer by ions is the major cause of PID.
FIGS. 1 and 2 are diagrams illustrating PID that is generated in the prior art.
Referring to FIG. 1, in the deposition and etch processes using plasma, excited molecules, radicals, and fractions of ions Ji and electrons Je exist within plasma generated by the supply of source gas. These electrons Je and ions Ji are incident on a wafer 100 with constant energy. At this time, an amount of electrons Je and an amount of ions Ji, which are incident on the wafer 100, are equal to each other. However, due to a difference of velocity distribution, almost all the ions Ji are incident vertically on the surface of the wafer 100, while the electrons Je are incident at a predetermined angle with respect to the surface of the wafer 100. Accordingly, the charging of the ions Ji and the electrons Je may be evenly distributed in a case in which a structure, such as patterns, does not exist on the wafer 100, but the charging of the ions Ji and the electrons Je may be unevenly distributed in a case in which patterns do exist on the wafer 100.
More specifically, as illustrated in FIG. 2, in a case in which a structure, such as patterns 210, exists on a wafer 200, since most of the ions Ji are incident vertically on the surface of the wafer 200, an amount of ions Ji incident on the surface of the wafer 200 is not greatly changed. However, in the case of electrons Je, the incident path of the electrons Je is blocked by the patterns 210. Thus, the electrons Je may not reach the wafer 200 between the patterns 210, because they bounce off the patterns 210. Accordingly, the number of the electrons Je which are incident on the wafer 200 between the patterns 210 may be reduced. Instead, the electrons Je incident on the walls of the patterns 210 may be increased as compared to the ions Ji, and the upper sides of the patterns 210 may be charged with negative (−) electric charges. As a result, in a normal state, the surface of the wafer 200 between the patterns 210 may be charged with positive (+) electric charges of the ions Ji. Such a phenomenon is becoming a more serious concern because the patterns 210 are formed in a finer shape as the integration density of the semiconductor device increases. Therefore, in a case in which the wafer 200 is electrically insulated, portions at which the patterns 210 and the surface of the wafer 200 are contacted with each other are charged with positive (+) electric charges, whereas the sides of the patterns 210 are charged with negative (−) electric charges.
In addition, the plasma itself has spatial nonuniformity according to the environment of the equipment itself or plasma conditions. In such cases, charging density nonuniformity of the wafer may be even more seriously.
In most cases, the deposition and etch processes using plasma are performed on the surface of a nonconductive material, for example, an insulation material such as silicon oxide (SiO2). As described above, as the charging density is uniformly formed, an electric current is generated from a low-charging-density side to a high-charging-density side so as to resolve the nonuniform charging density. Such an electric current flows through an element inside the wafer, for example, a gate dielectric layer. Thus, electric stress is applied to the semiconductor device, and PID such as an electron trap and a leakage current path is caused within the gate dielectric layer.
More specifically, a strong electric field may be formed in a thin metal interconnection by the nonuniform charging density, and thus, the metal interconnection may become molten.
In addition, the strong electric field increases a potential difference between a gate and a bulk, and the gate dielectric layer is broken accordingly.
Furthermore, the nonuniform charging density influences a threshold voltage of a transistor, and characteristics of the transistor are changed accordingly.
In the prior art aimed at preventing PID, the nonuniform charging density is accounted for by inserting a protection diode to form an artificial ion discharging path.
According to the prior art, in a case in which a well area is large, a protection diode is formed in an individual junction. In particular, since the well of the semiconductor device has a large area, it needs to be protected from PID using a separate protection device. Thus, a PID-prevention diode junction is formed in each junction.
However, the prior art is disadvantageous in that a layout area is greatly increased due to the insertion of the protection diode.
In addition, the prior art is disadvantageous in that an active region should be formed so as to form a hole for the insertion of the diode, and thus, an overall area is increased as much as the active region.